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RT8036 1 ds8036-02 april 2011 www.richtek.com ordering information note : richtek products are : ` rohs compliant and compatible with the current require- ments of ipc/jedec j-std-020. ` suitable for use in snpb or pb-free soldering processes. pin configurations wqfn-20l 3x3 (top view) one step down dc/dc converter and four linear regulators with individual on/off control general description the RT8036 is an integrated power management unit which integrates one 600ma high efficiency step down dc/dc converter and four low dropout voltage regulators with 300ma current capability for each regulator. the RT8036 is optimized for sub block power requirement solution. the individual on/off control for each device can provide flexibility for different power on sequence. four linear regulators provide high psrr output and are suitable for both analog and digital power. the RT8036 is available in the wqfn-20l 3x3 package that is suitable for portable device. features z z z z z four low noise ldos for up to 300ma z z z z z one high efficiency synchronous buck up to 600ma output z z z z z individual on/off control for each output z z z z z small 20-lead wqfn package z z z z z rohs compliant and halogen free applications z smart handheld device z cellular phone vinb enl2 vinl1 enl1 voutl3 voutl4 enl4 agnd pgnd enb voutb voutl2 voutl1 agnd nc 15 14 13 12 17 18 19 20 1 2 3 4 9 8 7 6 gnd 21 11 5 vinl2 16 lx enl3 pgnd 10 pgnd RT8036 package type qw : wqfn-20l 3x3 (w-type) lead plating system g : green (halogen free and pb free) output voltage : a : buck : 1v ldo1/2/3/4 : 1v/2.6v/3v/3.3v b : buck : 1.2v ldo1/2/3/4 : 1.8v/2.8v/2.8v/2.8v c : buck : 1.3v ldo1/2/3/4 : 1.8v/2.8v/2.8v/2.8v d : buck : 1.3v ldo1/2/3/4 : 1.8v/2.8v/2.8v/3.0v e : buck : 1.3v ldo1/2/3/4 : 1.8v/2.8v/2.8v/3.3v marking information for marking information, contact our sales representative directly or through a richtek distributor located in your area.
RT8036 2 ds8036-02 april 2011 www.richtek.com functional pin description pin no. pin name pin function 1 vinl1 supply input for ldo1 and ldo2. 2 enl1 chip enable for ldo1 (active high). 3 enl2 chip enable for ldo2 (active high). 4 vinb supply input for buck c onverter. 5 lx power switching output. 6, 8, 10 pgnd power ground. 7 enb chip enable for buck converter (active high). 9 voutb feedback input of buck converter. 11 enl3 chip enable for ldo3 (active high). 12 enl4 chip enable for ldo4 (active high). 13, 17 agnd analog ground. 14 voutl4 ldo4 output. 15 voutl3 ldo3 output. 16 vinl2 supply input for ldo3 and ldo4. 18 nc no internal connection. 19 voutl1 ldo1 output. 20 voutl2 ldo2 output. 21 (exposed pad) gnd ground. the exposed pad must be soldered to a large pc b and connected to agnd for maximum power dissipation. typical application circuit vinb enl2 vinl1 enl1 voutl3 voutl4 enl4 agnd enb voutb voutl2 voutl1 vinl2 lx enl3 pgnd RT8036 c outl1 1f c outl2 1f c outl3 1f c outl4 1f v out1 v out4 v out3 v out2 v outb c outb 10f l 2.2h c inl1 1f c inl2 1f chip enable c inb 4.7f v inb v inl1 v inl2 15 14 13, 17 12 19 20 1 2 3 4 9 7 6, 8, 10 11 5 16
RT8036 3 ds8036-02 april 2011 www.richtek.com function block diagram mux current detector current source controller driver control logic current limit detector current sense pwm comparator r c comp slope compensation osc & shutdown control ea uvlo &power good detector r s1 r s2 v ref mos driver shutdown and logic control current limit and thermal protection ea v ref mos driver shutdown and logic control current limit and thermal protection ea v ref mos driver shutdown and logic control current limit and thermal protection ea v ref mos driver shutdown and logic control current limit and thermal protection ea v ref vinb enl2 vinl1 enl1 voutl3 voutl4 enl4 pgnd enb voutb voutl2 voutl1 agnd vinl2 lx enl3
RT8036 4 ds8036-02 april 2011 www.richtek.com electrical characteristics to be continued recommended operating conditions (note 4) z supply voltage, v inb , v inl1 , v inl2 ------------------------------------------------------------------------ 2.5v to 5.5v z junction temperature range ------------------------------------------------------------------------------- ? 40 c to 125 c z ambient temperature range ------------------------------------------------------------------------------- ? 40 c to 85 c absolute maximum ratings (note 1) z buck supply input voltage, v inb ------------------------------------------------------------------------- ? 0.3v to 6.5v z enb, voutb v oltage --------------------------------------------------------------------------------------- ? 0.3v to v inb z ldo1, ldo2 supply input voltage, v inl1 , v inl2 ------------------------------------------------------ ? 0.3v to 6v z enl1 to enl4, vout1 to vout4 v oltage ------------------------------------------------------------- ? 0.3v to 6v z power dissipation, p d @ t a = 25 c wqfn ? 20l 3x3 ----------------------------------------------------------------------------------------------- 1.471w z package thermal resistance (note 2) wqfn ? 20l 3x3, ja ----------------------------------------------------------------------------------------- 68 c/w wqfn ? 20l 3x3, jc ----------------------------------------------------------------------------------------- 7.5 c/w z lead temperature (soldering, 10 sec.) ------------------------------------------------------------------ 260 c z junction temperature ---------------------------------------------------------------------------------------- 150 c z storage temperature range ------------------------------------------------------------------------------- ? 65 c to 165 c z esd susceptibility (note 3) hbm (human body mode) --------------------------------------------------------------------------------- 2kv mm (ma chine mode) ----------------------------------------------------------------------------------------- 200v (v inb = 3.6v, v inlx = v outlx + 0.7v, v enlx = v inlx , c inb = 4.7 f, c outb = 10 f, c inlx = c outlx = 1 f, l = 2.2 h, t a = 25 c, unless otherwise specified) parameter symbol test conditions min typ max unit buck converter input voltage range v inb 2.5 -- 5.5 v quiescent current i qb i ou tb = 0ma, -- 40 60 a shutdown current i shdnb enb = gnd -- 0.1 0.9 a output voltage accuracy v outb v inb = v outb + v to 5.5v v in > 2.5v which ever is larger. (note 5) ? 3 -- 3 % voutb pin input current i outb v outb = v inb ? 50 -- 50 na i ou tb = 200ma, v inb = 3.6v 0.1 0.28 0.6 r ds(on) of p-mosfet r ds(on)_p i ou tb = 200ma, v inb = 2.5v 0.1 0.38 0.6 i ou tb = 200ma, v inb = 3.6v 0.1 0.25 0.55 r ds(on) of n-mosfet r ds(on)_n i ou tb = 200ma, v inb = 2.5v 0.1 0.35 0.55 p-channel current limit i lim_p v inb = 2.5v to 5.5v 600 1800 2500 ma enb high-level input voltage v enb_h v inb = 2.5v to 5.5v 1.5 -- vinb v enb low-level input voltage v enb_l v inb = 2.5v to 5.5v -- -- 0.4 v under voltage lock out uvlo -- 1.8 -- v
RT8036 5 ds8036-02 april 2011 www.richtek.com parameter symbol test conditions min typ max unit under voltage lockout hysteresis uvlo_hys 0.05 0.1 0.35 v oscillator frequency f os c v inb = 3.6v, i ou tb = 100ma -- 1.5 -- mhz thermal shutdown temperature t sdb -- 160 -- c maximal duty cycle 100 -- -- % lx leakage current v inb = 3.6v, v lx = 0v or v lx = 3.6v 1 -- 100 a ldo ldo input voltage v inl = 2.5v to 5.5v 2.5 -- 5.5 v quiescent current i ql v enl > 1.5v -- 50 80 a shutdown current i ql _sd v enl < 0.4v -- 0.1 0.8 a dropout voltage (note 5) v drop i outl = 300ma -- 330 500 mv voutl accuracy v i outl = 1ma ? 3 -- 3 % line regulation v line v in = 2.5v to 5.5v 0 0.02 0.2 %/v load regulation v load 1ma < i outl < 300ma 0 0.1 0.6 % current limit i lim r load = 1 330 430 600 ma v ihl v inl = 2.5v to 5.5v, power on 1.5 -- -- v enl threshold v ill v inl = 2.5v to 5.5v, shutdown -- -- 0.4 v output voltage tc -- 100 -- ppm/c voutl discharge resistance in shutdown v in = 5v, en1 = en2 = gnd -- 20 -- thermal shutdown t sdl -- 170 -- c thermal shutdown hysteresis t sdl -- 30 -- c f = 100hz, i load = 10ma -- 65 -- f = 1khz, i load = 10ma -- 60 -- f = 10khz, i load = 10ma -- 50 -- f = 100hz, i load = 150ma -- 65 -- f = 1khz, i load = 150ma -- 50 -- psrr v inl = v outl + 1v c outl = 2.2 f i load = 50ma psrr f = 10khz, i load = 150ma -- 50 -- db note 1. stresses listed as the above ? absolute maximum ratings ? may cause permanent damage to the device. these are for stress ratings. functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may remain possibility to affect device reliability. note 2. ja is measured in the natural convection at t a = 25 c on a high effective four layers thermal conductivity test board of jedec 51-7 thermal measurement standard. the case point of jc is on the expose pad of the package. note 3. devices are esd sensitive. handling precaution is recommended. note 4. the device is not guaranteed to function outside its operating conditions. note 5. v = i out x r ds(on)_p
RT8036 6 ds8036-02 april 2011 www.richtek.com typical operating characteristics for buck en threshold vs. temperature 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 1.6 -40 -25 -10 5 20 35 50 65 80 95 110 125 temperature en voltage (v) ( c) v inb = 3.6v, v outb = 1.2v, i outb = 0a rising falling en threshold vs. input voltage 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 1.6 2.52.83.13.43.7 4 4.34.64.95.25.5 input voltage (v) en voltage (v) v outb = 1.2v, i outb = 0a rising falling uvlo threshold vs. temperature 1.3 1.4 1.5 1.6 1.7 1.8 1.9 2.0 2.1 -40 -25 -10 5 20 35 50 65 80 95 110 125 temperature input voltage (v) ( c) v outb = 1.2v, i outb = 0a rising falling output voltage vs. temperature 1.15 1.16 1.17 1.18 1.19 1.20 1.21 1.22 1.23 1.24 1.25 -40 -25 -10 5 20 35 50 65 80 95 110 125 temperature output voltage (v) ( c) v inb = 3.6v, i outb = 0a efficiency vs. output current 0 10 20 30 40 50 60 70 80 90 100 0.001 0.01 0.1 1 output current (a) efficiency (%) v outb = 1.2v, c out = 10uf, l = 2.2h v inb = 3.6v v inb = 5v output voltage vs. output current 1.200 1.202 1.204 1.206 1.208 1.210 1.212 1.214 1.216 1.218 1.220 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 output current (a) output voltage (v) v inb = 3.6v v inb = 5v
RT8036 7 ds8036-02 april 2011 www.richtek.com output ripple voltage time (500ns/div) v inb = 5v, v outb = 1.2v, i outb = 1a v outb (10mv/div) v lx (5v/div) output ripple voltage time (500ns/div) v inb = 3.6v, v outb = 1.2v, i outb = 1a v outb (10mv/div) v lx (5v/div) current limit vs. temperature 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 2.0 2.1 2.2 -40 -25 -10 5 20 35 50 65 80 95 110 125 temperature output current (a) v inb = 3.6v ( c) v inb = 5v v inb = 3.3v v outb = 1.2v current limit vs. input voltage 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 2.0 2.1 2.2 2.5 2.8 3.1 3.4 3.7 4 4.3 4.6 4.9 5.2 5.5 input voltage (v) output current (a) v outb = 1.2v frequency vs. temperature 1.20 1.25 1.30 1.35 1.40 1.45 1.50 1.55 1.60 -40 -25 -10 5 20 35 50 65 80 95 110 125 temperature frequency (mhz) v inb = 3.6v, v outb = 1.2v, i outb = 300ma ( c) frequency vs. input voltage 1.20 1.25 1.30 1.35 1.40 1.45 1.50 1.55 1.60 2.5 2.8 3.1 3.4 3.7 4 4.3 4.6 4.9 5.2 5.5 input voltage (v) frequency (mhz) v in = 3.6v, v out = 1.2v, i outb = 300ma
RT8036 8 ds8036-02 april 2011 www.richtek.com load transient response time (50 s/div) v inb = 3.6v, v outb = 1.2v i outb = 50ma to 0.5a v outb (50mv/div) i outb (500ma/div) load transient response time (50 s/div) v inb = 3.6v, v outb = 1.2v i outb = 50ma to 1a v outb (50mv/div) i outb (500ma/div) power off from en time (100 s/div) v inb = 3.6v, v outb = 1.2v, i outb = 1a v outb (1v/div) v enb (2v/div) i inb (500ma/div) power on from vin time (250 s/div) v enb = 3.6v, v outb = 1.2v, i outb = 1a v outb (1v/div) v inb (2v/div) i inb (500ma/div) power on from en time (100 s/div) v inb = 3.6v, v outb = 1.2v, i outb = 10ma v outb (1v/div) v enb (2v/div) i inb (500ma/div) power on from en time (100 s/div) v inb = 3.6v, v outb = 1.2v, i outb = 1a v outb (1v/div) v enb (2v/div) i inb (500ma/div)
RT8036 9 ds8036-02 april 2011 www.richtek.com load transient response time (50 s/div) v inb = 5v, v outb = 1.2v i outb = 50ma to 0.5a v outb (50mv/div) i outb (500ma/div) load transient response time (50 s/div) v inb = 5v, v outb = 1.2v i outb = 50ma to 1a v outb (50mv/div) i outb (500ma/div)
RT8036 10 ds8036-02 april 2011 www.richtek.com for ldo ldo1 output voltage vs. temperature 1.60 1.65 1.70 1.75 1.80 1.85 1.90 1.95 2.00 -40 -25 -10 5 20 35 50 65 80 95 110 125 temperature output voltage (v) ( c) v inl1 = 4.3v, no load ldo2 output voltage vs. temperature 2.60 2.65 2.70 2.75 2.80 2.85 2.90 2.95 3.00 -40 -25 -10 5 20 35 50 65 80 95 110 125 temperature output voltage (v) ( c) v inl1 = 4.3v, no load quiescent current vs. temperature 0 10 20 30 40 50 60 -40 -25 -10 5 20 35 50 65 80 95 110 125 temperature quiescent current (ua) ( c) v inl1 = 4.3v ldo2 dropout voltage vs. load current 0 50 100 150 200 250 300 350 400 450 0 25 50 75 100 125 150 175 200 load current (ma) dropout voltage (mv) v outl2 = 2.8v 125 c 25 c -40 c v outl1 = 1.8v, v outl2 = 2.8v, i outl1 = i outl2 = 1ma line transient response v inl1 (v) time (100 s/div) v outl2 (20mv/div) 4.8 3.8 v outl1 (20mv/div) v outl1 = 1.8v, v outl2 = 2.8v, i outl1 = i outl2 = 10ma line transient response v inl1 (v) time (100 s/div) v outl2 (20mv/div) 4.8 3.8 v outl1 (20mv/div)
RT8036 11 ds8036-02 april 2011 www.richtek.com power off from enl1 time (25 s/div) v outl2 (1v/div) v outl1 (1v/div) enl1 (5v/div) v inl1 = 5v, v outl1 = 1.8v, v outl2 = 2.8v, i outl1 = i outl2 = 50ma i outl1 = i outl2 = 10ma to 100ma load transient response time (250 s/div) v outl 2 (20mv/div) v outl1 (20mv/div) i out (100ma/div) v inl1 = 4.3v, v outl1 = 1.8v, v outl2 = 2.8v power on from enl1 time (25 s/div) v outl2 (1v/div) v outl1 (1v/div) enl1 (5v/div) v inl1 = 5v, v outl1 = 1.8v, v outl2 = 2.8v, i outl1 = i outl2 = 50ma i outl1 = i outl2 = 10ma to 50ma load transient response time (250 s/div) v outl2 (20mv/div) v outl1 (20mv/div) i out (50ma/div) v inl1 = 4.3v, v outl1 = 1.8v, v outl2 = 2.8v v outl1 = 1.8v, v outl2 = 2.8v, i outl1 = i outl2 = 100ma line transient response time (100 s/div) v outl2 (10mv/div) 4.8 3.8 v outl1 (10mv/div) v inl1 (v) v outl1 = 1.8v, v outl2 = 2.8v, i outl1 = i outl2 = 50ma line transient response time (100 s/div) v outl2 (20mv/div) 4.8 3.8 v outl1 (20mv/div) v inl1 (v)
RT8036 12 ds8036-02 april 2011 www.richtek.com voutl2 psrr -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 10 10 100 1000 10000 100000 1000000 frequency (hz) psrr (db) v inl2 = v enl2 = 4.3v 50mv, v outl2 = 2.8v, i outl2 = 50ma i outl2 = 10ma i outl2 = 150ma voutl1 psrr -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 10 10 100 1000 10000 100000 1000000 frequency (hz) psrr(db) v inl1 = v enl1 = 4.3v 50mv, v outl1 = 1.8v, i outl1 = 50ma i outl1 = 10ma i outl1 = 150ma noise time (10ms/div) v outl2 (100 v/div) v inl2 = v enl2 = 5v, i outl2 = 50ma noise time (10ms/div) v outl1 (100 v/div) v inl1 = v enl1 = 5v, no load
RT8036 13 ds8036-02 april 2011 www.richtek.com application information the RT8036 is an integrated power management ic including one buck converter and four linear regulators. the RT8036 features a fixed output voltage to eliminate the need of external feedback resistors and simplify the pcb layout. the RT8036 fix the output voltage by internal resistor and keep the output voltage between -3% to 3%. please refer to the ordering information for detailed output voltage setting. buck enable control pull the enb pin (>1.5v) to turn on the buck converter and to pull low the enb pin (<0.4v) to turn off the buck converter. soft-start the RT8036 has a soft-start to control the output voltage rise time and limit the current surge at the startup. the soft-start will begin while en rises above high threshold. buck current limiting a current limit feature allows the RT8036 to protect itself and external components during overload conditions. in operating mode, the inductor peak current under 600ma is normally used. the current limit prevents the loss of current control seen in some products when the output voltage is pulled low in serious overload conditions. inductor selection for a given input and output voltage, the inductor value and operating frequency determine the ripple current. the ripple current, i l , increases with higher v inb and decreases with higher inductance. out out l in vv i1 fl v ?? ?? = ? ?? ?? ?? ?? having a lower ripple current reduces the esr losses in the output capacitors and the output voltage ripple. highest efficiency operation is achieved at low frequency with small ripple current. this, however, requires a large inductor. a reasonable starting point for selecting the ripple current is i l = 0.4 (i max ). the largest ripple current occurs at the highest vinb. to guarantee that the ripple current stays below a specified maximum, the inductor value should be chosen according to the following equation : out out l(max) in(max) vv l1 fi v ??? ? =? ??? ? ??? ? ??? ? inductor core selection once the value for l is known, the type of inductor must be selected. high efficiency converters generally cannot afford the core loss found in low cost powdered iron cores, forcing the use of more expensive ferrite or mollypermalloy cores. actual core loss is independent of core size for a fixed inductor value but it is very dependent on the inductance selected. as the inductance increases, core losses decrease. unfortunately, increased inductance requires more turns of wire and therefore copper losses will increase. ferrite designs have very low core losses and are preferred at high switching frequencies, so design goals can concentrate on copper loss and preventing saturation. ferrite core material saturates ? hard ? , which means that inductance collapses abruptly when the peak design current is exceeded. this results in an abrupt increase in inductor ripple current and consequent output voltage ripple. do not allow the core to saturate! different core materials and shapes will change the size/ current and price/current relationship of an inductor. toroid or shielded pot cores in ferrite or permalloy materials are small and don't radiate energy but generally cost more than powdered iron core inductors with similar characteristics. the choice of which style inductor to use mainly depends on the price vs size requirements and any radiated field/emi requirements. c inb and c outb selection the input capacitance, c inb , is needed to filter the trapezoidal current at the source of the top mosfet. to prevent large ripple voltage, a low esr input capacitor sized for the maximum rms current should be used. rms current is given by : outb inb rms outb(max) inb outb v v ii 1 vv =?
RT8036 14 ds8036-02 april 2011 www.richtek.com this formula has a maximum at v inb = 2v outb , where i rms = i outb /2. this simple worst-case condition is commonly used for design because even significant deviations do not offer much relief. choose a capacitor rated at a higher temperature than required. several capacitors may also be paralleled to meet size or height requirements in the design. the selection of c outb is determined by the effective series resistance (esr) that is required to minimize voltage ripple and load step transients, as well as the amount of bulk capacitance that is necessary to ensure that the control loop is stable. loop stability can be checked by viewing the load transient response as described in a later section. the output ripple, v outb , is determined by : out l out 1 v i esr 8fc ?? ?? + ?? ?? the output ripple is highest at maximum input voltage since dil increases with input voltage. multiple capacitors placed in parallel may be needed to meet the esr and rms current handling requirements. dry tantalum, special polymer, aluminum electrolytic and ceramic capacitors are all available in surface mount packages. special polymer capacitors offer very low esr but have lower capacitance density than other types. tantalum capacitors have the highest capacitance density but it is important to only use types that have been surge tested for use in switching power supplies. aluminum electrolytic capacitors have significantly higher esr but can be used in cost-sensitive applications provided that consideration is given to ripple current ratings and long term reliability. ceramic capacitors have excellent low esr characteristics but can have a high voltage coefficient and audible piezoelectric effects. the high q of ceramic capacitors with trace inductance can also lead to significant ringing. using ceramic input and output capacitors higher values, lower cost ceramic capacitors are now becoming available in smaller case sizes. their high ripple current, high voltage rating and low esr make them ideal for switching regulator applications. however, care must be taken when these capacitors are used at the input and output. when a ceramic capacitor is used at the input and the power is supplied by a wall adapter through long wires, a load step at the output can induce ringing at the input, vinb. at best, this ringing can couple to the output and be mistaken as loop instability. at worst, a sudden inrush of current through the long wires can potentially cause a voltage spike at vinb large enough to damage the part. ldo capacitor selection like any low-dropout regulator, the external capacitors used with the RT8036 must be carefully selected for regulator stability and performance. using a capacitor whose value is >1 f on the RT8036 input and the amount of capacitance can be increased without limit. the input capacitor must be located at a distance of not more than 0.5 inch from the input pin of the ic and returned to a clean analog ground. any good quality ceramic or tantalum can be used for this capacitor. the capacitor with larger value and lower esr (equivalent series resistance) provides better psrr and line-transient response. the output capacitor must meet both requirements for minimum amount of capacitance and esr in all ldos application. the RT8036 is designed specifically to work with low esr ceramic output capacitor in space-saving and performance consideration. using a ceramic capacitor whose value is at least 1 f with esr is > 20m on the RT8036 output ensures stability. the RT8036 still works well with output capacitor of other types due to the wide stable esr range. figure 1. shows the curves of allowable esr range as a function of load current for various output capacitor values. output capacitor of larger capacitance can reduce noise and improve load transient response, stability, and psrr. the output capacitor should be located not more than 0.5 inch from the output pin of the RT8036 and returned to a clean analog ground. ldo enable the ldo of RT8036 goes into shutdown mode when the enl1, enl2, enl3 and enl4 pin is in a logic low condition. during this condition, the pass transistor, error amplifier, and bandgap are turned off, reducing the supply current to be lower than 1 a. the enl1, enl2, enl3 and enl4 pin can be directly tied to vinl1 and vinl2 to keep the part on.
RT8036 15 ds8036-02 april 2011 www.richtek.com figure 1. stable region of output capacitor esr ldo current limit the RT8036 contains an independent current limiter, which monitors and controls the pass transistor's gate voltage, limiting the output current to 460ma (typ.). the output can be shorted to ground indefinitely without damaging the part. thermal shutdown protection as the die temperature reaches a certain thermal shutdown threshold, the chip will enter protection mode. the power mosfet will turn-off during protection mode to prevent abnormal operation. thermal considerations for continuous operation, do not exceed absolute maximum operation junction temperature. the maximum power dissipation depends on the thermal resistance of ic package, pcb layout, the rate of surroundings airflow and temperature difference between junction to ambient. the maximum power dissipation can be calculated by following formula : p d(max) = (t j(max) ? t a ) / ja where t j(max) is the maximum operation junction temperature, t a is the ambient temperature and the ja is the junction to ambient thermal resistance. for recommended operating conditions specification of RT8036, the maximum junction temperature is 125 c. the junction to ambient thermal resistance ja is layout dependent. for wqfn-20l 3x3 packages, the thermal resistance ja is 68 c/w on the standard jedec 51-7 four layers thermal test board. the maximum power dissipation at t a = 25 c can be calculated by following formula : p d(max) = (125 c ? 25 c) / (68 c/w) =1.471w for wqfn-20l 3x3 packages the maximum power dissipation depends on operating ambient temperature for fixed t j(max) and thermal resistance ja . for RT8036 packages, the figure 2 of derating curves allows the designer to see the effect of rising ambient temperature on the maximum power allowed. 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 0 25 50 75 100 125 ambient temperature (c) maximum power dissipation (w) four layers pcb wqfn-20l 3x3 0.001 0.01 0.1 1 10 100 0 50 100 150 200 250 300 load current (ma) region of stable c out esr ( ? ) unstable range stable range simulation verify v inl = 5v, c inl = c outlx = 1uf/x7r figure 2. derating curves for RT8036 packages layout consideration the RT8036 is an integrated power management unit which integrates one 1a high efficiency step down dc/dc converter and four low dropout voltage regulators with 300ma current capability for each regulator. careful pcb layout is necessary. for best performance, place all peripheral components as close to the ic as possible. a short connection is highly recommended. the following guidelines should be strictly followed when designing a pcb layout for the RT8036. ` input capacitor should be placed close to ic and connected to ground plane. the trace of input in the pcb should be placed far away from the sensitive devices or shielded by the ground.
RT8036 16 ds8036-02 april 2011 www.richtek.com ` the gnd should be connected to a strong ground plane for heat sinking and noise protection. ` the inductor should be placed close to lx pin and connected to output capacitor. the trace of input in the pcb should be placed far away from the sensitive devices or shielded by the ground. ` output capacitor should be placed close to inductor and connected to ground plane to reduce noise coupling. figure 3. pcb layout guide vinb enl2 vinl1 enl1 voutl3 voutl4 enl4 agnd pgnd enb voutb voutl2 voutl1 agnd nc 15 14 13 12 17 18 19 20 1 2 3 4 9 8 7 6 gnd 21 11 5 vinl2 16 lx enl3 pgnd 10 pgnd battery voutb gnd gnd input capacitor should be placed close to v in and connected to ground plane. the trace of v in in the pcb should be placed far away the sensitive devices or shielded by the ground. output capacitor should be placed close to v out and connected to ground plane to reduce noise coupling. input capacitor should be placed close to v in and connected to ground plane. the trace of v in in the pcb should be placed far away the sensitive devices or shielded by the ground. output capacitor should be placed close to v out and connected to ground plane to reduce noise coupling. the inductor (l) should be placed close to lx and connected to cout to reduce noise. c out2 c out1 c inl2 c inl1 c inb c out3 c out4
RT8036 17 ds8036-02 april 2011 www.richtek.com richtek technology corporation headquarter 5f, no. 20, taiyuen street, chupei city hsinchu, taiwan, r.o.c. tel: (8863)5526789 fax: (8863)5526611 information that is provided by richtek technology corporation is believed to be accurate and reliable. richtek reserves the ri ght to make any change in circuit design, specification or other related things if necessary without notice at any time. no third party intellectual property inf ringement of the applications should be guaranteed by users when integrating richtek products into any application. no legal responsibility for any said applications i s assumed by richtek. richtek technology corporation taipei office (marketing) 5f, no. 95, minchiuan road, hsintien city taipei county, taiwan, r.o.c. tel: (8862)86672399 fax: (8862)86672377 email: marketing@richtek.com outline dimension dimensions in millimeters dimensions in inches symbol min max min max a 0.700 0.800 0.028 0.031 a1 0.000 0.050 0.000 0.002 a3 0.175 0.250 0.007 0.010 b 0.150 0.250 0.006 0.010 d 2.950 3.050 0.116 0.120 d2 1.650 1.750 0.065 0.069 e 2.950 3.050 0.116 0.120 e2 1.650 1.750 0.065 0.069 e 0.400 0.016 l 0.350 0.450 0.014 0.018 w-type 20l qfn 3x3 package note : the configuration of the pin #1 identifier is optional, but must be located within the zone indicated. det ail a pin #1 id and tie bar mark options 1 1 2 2

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